The authors present a new DMA system where the CPU need not be kept inactive during the clock cycles where the direct memory access is performed. The method is especially interesting because it allows simultaneous data processing and transmission and in particular to the signal processing from integrated sensor systems (ISS). The procedure is based on the sharing of the RAM memory by the CPU and the DMA controller, so both of them can read or write in memory during the same clock cycle without conflict. This simple but powerful method is easily compatible with a multimicroprocessor system based on a shared memory structure.