| Автор | K Y Choi |
| Автор | J W Lee |
| Автор | H S Choi |
| Автор | J S Yu |
| Автор | M K Han |
| Автор | Y S Kim |
| Дата выпуска | 1997-01-01 |
| dc.description | The effects of two-step annealing on the device characteristics of polysilicon thin film transistors are investigated. The device characteristics such as drain current, mobility and threshold voltage of the low temperature furnace annealed polysilicon thin film transistors is improved considerably due to the reduction of in-grain defects by post-laser annealing. The post-high temperature furnace annealing (900°C) on the low temperature furnace annealed devices does not improve the device performance of polysilicon thin film transistors, due to the facts the annealing temperature of 900°C is much lower than the melting temperature (≥ 1300°C) of polysilicon. We have also found that the activation energy and hydrogen passivation rate in two-step annealed polysilicon thin film transistors is also improved significantly by the reduction of tail states due to the elimination of in-grain defects. |
| Формат | application.pdf |
| Издатель | Institute of Physics Publishing |
| Название | Effects of two-step annealing on the characteristics of the low temperature polycrystalline silicon thin film transistors |
| Тип | paper |
| DOI | 10.1088/0031-8949/1997/T69/022 |
| Electronic ISSN | 1402-4896 |
| Print ISSN | 0031-8949 |
| Журнал | Physica Scripta |
| Том | 1997 |
| Первая страница | 131 |
| Последняя страница | 133 |
| Выпуск | T69 |
