In order to free microelectromechanical systems and other microsystems from wire tethering, an inductive link with integrated receiving coil is shown to transfer power onto silicon chips. Link efficiency (ratio of power delivered to the load to power into the driving coil) benefits from receiver coils with both large interception areas and low resistances, contradictory conditions for integrated coils due to high specific resistance from planar fabrication. To address this, an ‘inlaid electroplating’ procedure is developed to fabricate microcoils on silicon substrates. Copper coils of 14 mm side length, 54 µm height and 100 µm pitch are electroplated and planarized to allow further lithography. Sidewalls between Cu lines are selectively removed to modify coil capacitances. Thin film and electroplated microcoils with and without sidewalls are characterized and compared as link receivers. Little difference in power delivery is observed between plated microcoils with and without sidewalls. Powering efficiency to a 50 Ω load reached 85% for a link coupling of ∼0.75. Since link properties are affected by parasitic effects from silicon chips, an equivalent circuit is developed, providing a good prediction of link efficiency. Link optimization is discussed using our model.