| Автор | Zhang Changchun |
| Автор | Wang Zhigong |
| Автор | Shi Si |
| Автор | Miao Peng |
| Автор | Tian Ling |
| Дата выпуска | 2009-09-01 |
| dc.description | A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 × 780 μm<sup>2</sup>. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system. |
| Формат | application.pdf |
| Издатель | Institute of Physics Publishing |
| Копирайт | 2009 Chinese Institute of Electronics |
| Название | 5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction |
| Тип | paper |
| DOI | 10.1088/1674-4926/30/9/095009 |
| Electronic ISSN | 2058-6140 |
| Print ISSN | 1674-4926 |
| Журнал | Journal of Semiconductors |
| Том | 30 |
| Первая страница | 95009 |
| Последняя страница | 95014 |
| Выпуск | 9 |
