Minimization algorithm for non-concurrent PLAs
DUECK†, GERHARD W.; BUTLER, JON T.; DUECK†, GERHARD W.; Department of Mathematics and Computer Science, St. Francis Xavier University; BUTLER, JON T.; Department of Electrical and Computer Engineering, Naval Postgraduate School
Журнал:
International Journal of Electronics
Дата:
1992
Аннотация:
In the design of certain self-checking programmable logic arrays (PLAs), at most one line is activated in the AND plane, such PLAs are termed non-concurrent. A heuristic algorithm for the minimization of non-concurrent PLAs is presented. It operates on two adjacent cubes, replacing them by one, two, and sometimes more than two cubes. The algorithm produces the best solutions known so far.
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