| Автор | DUECK†, GERHARD W. |
| Автор | BUTLER, JON T. |
| Дата выпуска | 1992 |
| dc.description | In the design of certain self-checking programmable logic arrays (PLAs), at most one line is activated in the AND plane, such PLAs are termed non-concurrent. A heuristic algorithm for the minimization of non-concurrent PLAs is presented. It operates on two adjacent cubes, replacing them by one, two, and sometimes more than two cubes. The algorithm produces the best solutions known so far. |
| Формат | application.pdf |
| Издатель | Taylor & Francis Group |
| Копирайт | Copyright Taylor and Francis Group, LLC |
| Название | Minimization algorithm for non-concurrent PLAs |
| Тип | research-article |
| DOI | 10.1080/00207219208925781 |
| Electronic ISSN | 1362-3060 |
| Print ISSN | 0020-7217 |
| Журнал | International Journal of Electronics |
| Том | 73 |
| Первая страница | 1113 |
| Последняя страница | 1119 |
| Аффилиация | DUECK†, GERHARD W.; Department of Mathematics and Computer Science, St. Francis Xavier University |
| Аффилиация | BUTLER, JON T.; Department of Electrical and Computer Engineering, Naval Postgraduate School |
| Выпуск | 6 |
